Architecture Evaluation for FPGAs with Embedded Memory

As the capacity of eld programmable gate arrays (FPGAs) increases, on-chip memories have become an essential component to provide high degree of on-chip integration. Modern FPGAs, such as Actel MX 27] and DX FPGAs 26], Altera FLEX10K, FLEX10KE 29] and APEX20K device family 30], and Vantis VF1 series FPGAs 28], provide embedded memory blocks (EMBs) to be used as on-chip memories. Compared with the distributed on-chip memory implementation , as that in Xilinx XC4000 series FPGAs, the dedicated EMBs result in denser memory implementation, but require the FPGA vendors to partition the chip for seperate logic and memory implementation. If a circuit design does not consume all of the available EMBs as on-chip memories , the chip area devoted to the unused memories could be completely wasted. However, it was shown that uncom-mitted EMBs can be eeciently used to implement logic for area minimization 1] 2]. 1] also guarantees that the circuit delay does not increase when using EMBs to minimize the circuit area. In addition, it was shown in 6] that EMBs can be taken as large look-up tables (LUTs) and used to eeec-tively minimize the circuit delay. With the algorithms developed in 1], 4] and 6], we present in this paper the studies on FPGA embedded memory block architecture evaluation. We shall explore how the sizes and the number of available embedded memory blocks aaect the circuit delay and area when these on-chip memories are used to implement logic functions. Extensive experiments and analysis are presented according to diierent design requirements, physical implementations, and the combination of several key design parameters within reasonable ranges. A number of interesting results are obtained. For example, our experimentation shows that EMBs with 512 memory bits lead to the best performance and area improvement in a 4-LUT based FPGA.